The present invention relates to a semiconductor integrated circuit device and a method of producing the same. More specifically, the invention relates to a semiconductor integrated circuit device having a mask ROM and to technology that can be effectively adapted to a method of producing the same.
The mask ROM's include a lateral mask ROM that is advantageous for high-speed operation and a vertical mask ROM that is advantageous for being highly densely integrated.
In the field of vertical mask ROM, a double-layer gate structure (multi-gate structure) has been employed for the purpose of accomplishing a highly dense integration. The vertical mask ROM of the double-layer gate structure has been disclosed in Japanese Patent Laid-Open No. 41188/1978.
The double-layer gate structure consists of second gate electrodes arranged among the first gate electrodes arranged in the direction of the gate length maintaining a predetermined distance. The first gate electrodes are composed of a gate electrode material (polycrystalline silicon film) of the first layer, and the second gate electrodes are composed of a gate electrode material (polycrystalline silicon film) of the second layer. Ends of the first gate electrodes and ends of the second gate electrodes have been overlapped by amounts that correspond to margin for aligning the mask in the step of manufacturing.
The thus constituted vertical mask ROM makes it possible to eliminate a portion that corresponds to the source region or the drain region between the first gate electrodes and the second gate electrodes. That is, the vertical mask ROM of this type enables the areas of the memory cell array to be reduced in the direction of gate length and, hence, enables the degree of integration to be increased.
The data are written onto the vertical mask ROM prior to forming the first gate electrodes and the second gate electrodes. That is, the data are written onto the vertical mask ROM in a way as described below.
First, impurities for writing data are selectively introduced into the channel forming regions in the main surface of a semiconductor substrate. The impurities for writing data form depletion-type MISFET of a conductivity type opposite to that of the semiconductor substrate.
Then, first gate electrodes and second gate electrodes are formed in positions in a region where the impurities for writing data are introduced.